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參數(shù)資料
| 型號： | ICSSSTUA32866BHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5.50 X 13.50 MM, LEAD FREE, MO-205, LFBGA-96 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ICSSSTUA32866BHLFT |
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22
ICSSSTUA32866B
1054A—01/28/05
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
-
410
MHz
tW
Pulse duration, CK, CK HIGH or LOW
1
-
ns
tACT
Differential inputs active time (See Notes 1 and 2)
-
10
ns
tINACT
Differential inputs inactive time (See Notes 1 and 3)
-
15
ns
tsu
Setup time
DSR# before CK
↑, CK#↓,
CSR# high
0.7
ns
tsu
Setup time
CSR# before CK
↑, CK#↓,
DCS# high
0.7
ns
tsu
Setup time
DCS# before CK
↑, CK#↓,
CSR# low
0.5
ns
tsu
Setup time
DODT, DCKE and data before
CK
↑, CK#↓
0.5
ns
tsu
Setup time
PAR_IN before CK
↑, CK#↓
0.5
ns
Hold time
DCS#, DODT, DCKE and Q
after CK
↑, CK#↓
0.50
ns
Hold time
PAR_IN after CK
↑, CK#↓
0.50
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
SYMBOL
Notes:
tH
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V
UNITS
PARAMETERS
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
fmax
Max input clock frequency
410
MHz
tPDM
Propagation delay, single
bit switching
CK
↑ to CK#↓ QN
1.1
1.9
ns
tPD
Propagation delay
CK
↑ to CK#↓ to PPO
0.5
1.8
ns
tLH
Low to High propagation
delay
CK
↑ to CK#↓ to QERR#
1.2
3
ns
tHL
High to low propagation
delay
CK
↑ to CK#↓ to QERR#
1
2.4
ns
tPDMSS
Propagation delay
simultaneous switching
CK
↑ to CK#↓ QN
-
2
ns
tPHL
High to low propagation
delay
Rst#
↓ to QN↓
3ns
tPHL
High to low propagation
delay
Rst#
↓ to PPO↓
3ns
tPLH
Low to High propagation
delay
Rst#
↓ to QERR#↑
3ns
2. Guaranteed by design, not 100% tested in production.
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