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參數(shù)資料
| 型號： | ICS950223YFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-118, SSOP-48 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 209K |
| 代理商： | ICS950223YFLFT |
12
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
I
2C Table: Vendor & Revision ID Register
Bit 7
RID3
R
-
1
Bit 6
RID2
R
-
1
Bit 5
RID1
R
-
0
Bit 4
RID0
R
-
1
Bit 3
VID3
R
-
0
Bit 2
VID2
R
-
0
Bit 1
VID1
R
-
0
Bit 0
VID0
R
-
1
I
2C Table: Byte Count Register
Bit 7
BC7
RW
-
0
Bit 6
BC6
RW
-
0
Bit 5
BC5
RW
-
0
Bit 4
BC4
RW
-
0
Bit 3
BC3
RW
-
1
Bit 2
BC2
RW
-
1
Bit 1
BC1
RW
-
1
Bit 0
BC0
RW
-
1
I
2C Table: Watchdog Timer Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
WD7
RW
-
0
Bit 6
WD6
RW
-
0
Bit 5
WD5
RW
-
0
Bit 4
WD4
RW
-
0
Bit 3
WD3
RW
-
1
Bit 2
WD2
RW
-
0
Bit 1
WD1
RW
-
0
Bit 0
WD0
RW
-
0
I
2C Table: VCO Control Select Bit & WD Timer Control Register
Bit 6
WDEN
Watchdog Enable
RW
Disable
Enable
0
Bit 4
WD SF4
RW
-
1
Bit 3
WD SF3
RW
-
1
Bit 2
WD SF2
RW
-
0
Bit 1
WD SF1
RW
-
0
Bit 0
WD SF0
RW
-
1
0
Bit 5
-
WDFSEN
WD Safe Frequency
Mode
RW
Latched
FS/Byte0
WD B10
b(4:0)
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 8 X 290ms
=2.32 seconds
-
PWD
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
-
01
PWD
Byte 8
Pin #
Name
Control Function
Type
0
1
IIC Prog.
B(11:17)
M/N Programming
Enable
RW
Type
0
1
Type
-
Byte 7
Pin #
Name
Control Function
REVISION ID
-
VENDOR ID
-
Byte 9
-
PWD
Bit 7
-M/NEN
0
Latched
Input
Byte 10
Pin #
Name
Control Function
-
Writing to these bit will
configure the safe
frequency as Byte 0 Bit
(6:0)
-
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