參數(shù)資料
型號(hào)： ICS950223YFLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 0.300 INCH, LEAD FREE, MO-118, SSOP-48
文件頁(yè)數(shù)： 18/24頁(yè)
文件大?。?/td> 209K
代理商： ICS950223YFLFT
3
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
Pin Description (Continued)
PIN PIN
PIN
#
NAME
TYPE
25
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
26
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
27
3V66_3_48MHz/Sel66_48#**
I/O
Selectable 66.66MHz, 48MHz clock output / Select input for 66.66/48MHz output.
0=48mHz, 1 = 66.66MHz
28
3V66_2
OUT 3.3V 66.66MHz clock output
29
GND
PWR Ground pin.
30
3V66_1
OUT 3.3V 66.66MHz clock output
31
3V66_0
OUT 3.3V 66.66MHz clock output
32
VDD3V66
PWR Power pin for the 3V66 clocks.
33
GND
PWR Ground pin.
34
AVDD
PWR 3.3V Analog Power pin for Core PLL
35
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
36
GNDCPU
PWR Ground pin for the CPU outputs
37
CPUCLKC1
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
38
CPUCLKT1
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
39
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
40
CPUCLKC0
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
41
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
42
PD#*
IN
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
43
GNDCPU
PWR Ground pin for the CPU outputs
44
CPUCLKC2
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
CPUCLKT2
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
46
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
47
GNDREF
PWR Ground pin for the REF outputs.
48
REF0/MULTSEL0**
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz
reference clock.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
DESCRIPTION
~ This output has 2X drive
相關(guān)PDF資料
PDF描述
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