參數(shù)資料
型號(hào)： ICS950227YFLFT
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 0.300 INCH, MO-118, SSOP-56
文件頁(yè)數(shù)： 1/17頁(yè)
文件大?。?/td> 128K
代理商： ICS950227YFLFT
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
Block Diagram
Pin Configuration
56-Pin 300-mil SSOP
Frequency Table
Recommended Application:
CK-408 clock Intel 845 with P4 processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
* These inputs have 150K internal pull-up resistor to VDD.
Programmable Timing Control Hub for P4
2
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VDDREF
1
56 REF
X1
2
55 FS1
X2
3
54 FS0
GND
4
53 CPU_STOP#*
PCICLK_F0
5
52 CPUCLKT0
PCICLK_F1
6
51 CPUCLKC0
PCICLK_F2
7
50 VDDCPU
VDDPCI
8
49 CPUCLKT1
GND
9
48 CPUCLKC1
PCICLK0 10
47 GND
PCICLK1 11
46 VDDCPU
PCICLK2 12
45 CPUCLKT2
PCICLK3 13
44 CPUCLKC2
VDDPCI 14
43 MULTSEL0*
GND 15
42 IREF
PCICLK4 16
41 GND
PCICLK5 17
40 FS2
PCICLK6 18
39 48MHz_USB
VDD3V66 19
38 48MHz_DOT
GND 20
37 VDD48
3V66_2 21
36 GND
3V66_3 22
35 3V66_1/VCH_CLK
3V66_4 23
34 PCI_STOP#*
3V66_5 24
33 3V66_0
*PD# 25
32 VDD3V66
VDDA 26
31 GND
GND 27
30 SCLK
Vtt_PWRGD# 28
29 SDATA
IC
S
950227
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
3V66 (5:2,0)
48MHz_DOT
3V66_1/VCH_CLK
X1
WDEN
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
Vtt_PWRGD#
FS (2:0)
I REF
Control
Logic
Config.
Reg.
REF
3
7
5
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
相關(guān)PDF資料
PDF描述
ICS950227YFT 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS950227YFLFT 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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