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參數(shù)資料
| 型號： | ICS950227YFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | ICS950227YFLFT |
11
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
mA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
Operating Supply Current
IDD3.3OP
CL = Full load
283
360
mA
Powerdown Current
IDD3.3PD
IREF=2.32 mA
23
25
mA
Input Frequency
Fi
VDD = 3.3 V
14.32
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
COUT
Output pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Clk Stabilization
1,2
TSTAB
From PowerUp or deassertion of
PowerDown to 1st clock.
1.8
ms
tPZH,tPZL
Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
Delay
1
Input Capacitance
1
Input Low Current
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