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參數(shù)資料
| 型號： | ICS950227YFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | ICS950227YFLFT |
5
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
I
2C Table: Frequency Select Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
SPREAD ENABLE
Frequency H/W IIC
Select
RW
OFF
ON
0
Bit 6
CENTER/DOWNSP
READ SELECT
CENTER/DOWNSPRE
AD SELECT
RW
DOWN
SPREAD
CENTER
SPREAD
0
Bit 5
3V66/VCH SELECT 48MHz/66.66MHz SEL
RW
66.66MHz
48.00MHz
0
Bit 4
CPU_STOP#
CPU STOP Read Back
R
X
Bit 3
PCI_STOP#
HW/SW SELECT
Freq Select Bit 3
RW/R
PCI STOP
PCI
RUNNING
1
Bit 2
FS2
Freq Select 2 Read
Back
RX
Bit 1
FS1
Freq Select 1 Read
Back
RX
Bit 0
FS0
Freq Select 0 Read
Back
RX
I
2C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
MULTSEL0
READBACK
RX
Bit 6
WD ALARM
Watchdog Alarm Read
Back
R
NO ALARM
ALARM SET
0
Bit 5
CPU2/CPUC2
RW
STOPPABLE FREE-RUN
0
Bit 4
CPU1/CPUC1
RW
STOPPABLE FREE-RUN
0
Bit 3
CPU0/CPUC0
RW
STOPPABLE FREE-RUN
0
Bit 2
CPU2/CPUC2
Output Control
RW
Disable
Enable
1
Bit 1
CPU1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPU0/CPUC0
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
RW
-
0
Bit 6
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
48MHz_DOT
Output Control
RW
Disable
Enable
1
Bit 6
48MHz_USB
Output Control
RW
Disable
Enable
1
Bit 5
PCIF2
RW
FREE-RUN STOPPABLE
0
Bit 4
PCIF1
RW
FREE-RUN STOPPABLE
0
Bit 3
PCIF0
RW
FREE-RUN STOPPABLE
0
Bit 2
PCICLK_F2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK_F0
Output Control
RW
Disable
Enable
1
5
7
6
5
READBACK
Byte 1
43
READBACK
53
34
40
55
54
READBACK
Byte 0
-
35
-
45, 44
49, 48
52, 51
17
16
13
Byte 2
-
18
45, 44
49, 48
52, 51
12
11
10
6
Byte 3
38
39
7
CPU FREE-RUN NING
CONTROL
CPU FREE-RUN NING
CONTROL
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