參數(shù)資料
型號(hào)： ICS950223YFLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 0.300 INCH, LEAD FREE, MO-118, SSOP-48
文件頁(yè)數(shù)： 2/24頁(yè)
文件大?。?/td> 209K
代理商： ICS950223YFLFT
10
Integrated
Circuit
Systems, Inc.
ICS950223
0496C—05/06/05
I
2
C Table: Frequency Select Register
Bit 7
FS Source
Frequency H/W IIC
Select
RW
Latch Inputs
IIC
0
Bit 6
FS6
Freq Select Bit 6
RW
0
Bit 5
FS5
Freq Select Bit 5
RW
0
Bit 4
FS4
Freq Select Bit 4
RW
0
Bit 3
FS3
Freq Select Bit 3
RW
0
Bit 2
FS2
Freq Select Bit 2
RW
0
Bit 1
FS1
Freq Select Bit 1
RW
0
Bit 0
FS0
Freq Select Bit 0
RW
0
I
2
C Table: Spreading and Device Behavior Control Register
Bit 7
SS1
Spread Select 1
RW
0
Bit 6
SS0
Spread Select 0
RW
0
Bit 4
WDS_Status
WD Soft Alarm Status
RW
Normal
Alarm
0
Bit 3
Reserved
RW
-
1
Bit 2
CPUT2/CPUC2
Output Control
RW
Disable
Enable
1
Bit 1
CPUT1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPUT0/CPUC0
Output Control
RW
Disable
Enable
1
SS_EN
Spread Enable Control
RW
OFF
Control Function
Type
0
1
1PWD
0
See Table 1: QuadRom
Frequency Selection Table
PWD
See Table 2: Spread
Spectrum Table
ON
1
Name
Type
-
Byte 0
-
Pin #
Control Function
-
Name
-
45/44
-
Byte 1
Pin #
Bit 5
-
38/37
41/40
Table2: Spread Spectrum Select
SS1
SS0
(Byte 1 bit 7)
(Byte 1 bit 6)
0
0.35%
Spread 1
0
1
0.50%
Spread 2
1
0
0.75%
Spread 3
1
1.00%
Spread 4
Spread %
Note
I
2
C Table: Output Control Register
Bit 7
AEN#
3V66/PCI Freq Source
Select
RW
CPU_PLL
Sync
FIX_PLL
Async
0
Bit 6
PCICLK9
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK8
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK7
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK3
Output Control
RW
Disable
Enable
1
1PWD
12
11
Name
Control Function
Type
0
17
16
-
Byte 2
Pin #
15
14
10
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