參數資料
型號: ICS9248YF-175LF-T
元件分類: 時鐘產生/分配
英文描述: 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, SSOP-48
文件頁數: 9/13頁
文件大小: 355K
代理商: ICS9248YF-175LF-T
5
ICS9248-175
Advance Information
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
#
0
S
F
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
0
#
1
S
F
3
t
i
B0
41
T
U
O
_
M
A
R
D
S
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B3
4
,
4
41
O
T
K
L
C
U
P
C
,
0
C
K
L
C
U
P
C
.
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a
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(
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b
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)
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m
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"
0
t
i
B6
41
e
l
b
a
n
e
1
T
K
L
C
U
P
C
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
#
2
S
F
6
t
i
B7
1
0
K
L
C
I
C
P
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B3
11
5
K
L
C
I
C
P
3
t
i
B2
11
4
K
L
C
I
C
P
2
t
i
B1
11
3
K
L
C
I
C
P
1
t
i
B0
11
2
K
L
C
I
C
P
0
t
i
B8
1
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
3
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
1
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
0
t
i
B
-
1)
d
e
v
r
e
s
e
R
(
Byte 4: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B-
1
#
E
D
O
M
3
t
i
B-
0
#
3
S
F
2
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B8
41
1
F
E
R
0
t
i
B2
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this register
can cause malfunction
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B-
0
z
H
M
8
4
_
L
E
S
5
t
i
B6
21
z
H
M
8
4
t
i
B5
21
z
H
M
8
4
_
4
2
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
,
0
2
,
7
1
2
1)
8
:
1
(
M
A
R
D
S
1
t
i
B
,
9
2
,
8
2
3
,
1
3
1)
4
:
7
(
M
A
R
D
S
0
t
i
B
,
5
3
,
4
3
8
3
,
7
3
1)
0
:
3
(
M
A
R
D
S
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