參數(shù)資料
型號(hào)： ICS9248YF-179-T
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 166.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 0.300 INCH, SSOP-48
文件頁(yè)數(shù)： 1/15頁(yè)
文件大小： 233K
代理商： ICS9248YF-179-T
ICS9248-179
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
9248-179 Rev B 08/22/01
Frequency Generator for Intel Pentium III Celeron Processor
Block Diagram
Recommended Application:
Single chip clock solution for SIS 635/640 Intel Pentium III
Celeron chipset.
Output Features:
2 - CPUs @ 2.5V.
1 - IOAPIC @ 2.5V.
1 - SDRAM @ 3.3V
6- PCI @3.3V
2 - AGP @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2C
(Default is 24MHz)
2- REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I
2C read back.
Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I
2C programming.
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
Uses external 14.318MHz crystal
Skew Specifications:
CPU - CPU: < 175ps
PCI - PCI: < 500ps
CPU - SDRAM: < 250ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
AGP - AGP: <175ps
CPU - AGP: 1-4ns
Functionality
Pin Configuration
48-Pin 300mil SSOP
*
These are double strength.
** (1X/2X) have single or double strength to
drive 2 loads.
1. Internal pull-up, of 120K to VDD.
2. These inputs have a 120K pull down to GND.
VDDREF
REF0
*FS1/REF1
GND
X1
X2
GND
VDDPCI
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
VDDAGP
AGPCLK0
AGPCLK1
GND
VDD48
48MHz
AGPSEL/ 24_48MHz
GND
2
*FS0/
2
21
FS2/PCICLK_F
FS3/PCICLK0
**FS4/
**
2
VDDLAPIC
IOAPIC*
GND
VDDL
CPUCLK0
NC
GND
VDDL
CPUCLK1
GND
NC
VDDSDR
SDRAM
GND
PCI_STOP#
CPU_STOP#
PD#
SDRAM_STOP#
AGP_STOP#
SDATA
SCLK
GND
VDD
2
1
2
ICS9248-179
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (1:0)
SDRAM
PCICLK (4:0)
AGP (1:0)
IOAPIC
PCICLK_F
2
5
2
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
AGP_STOP#
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
AGP
DIVDER
Stop
IOAPIC
DIVDER
Preliminary Product Preview
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
00
66.66
33.33
66.66
50
00
01
100
33.33
66.66
50
00
10
166.66
33.33
66.66
55.6
00
11
133.33
33.33
66.66
50
01
00
66.66
100
33.33
66.66
50
01
100
66.66
33.33
66.66
50
01
10
100
133.33
33.33
66.66
50
01
11
133.33
100
33.33
66.66
50
10
00
112
33.6
67.2
56
10
01
124
31
62
46.5
10
138
34.5
69
46.0
10
11
150
30
60
50
11
00
66.66
133.33
33.33
66.66
49.84
11
01
133.33
166.66
33.33
66.66
55.3
11
10
150
100
30
60
50
11
160
120
30
60
48
AGP SEL
= 0
AGP SEL
= 1
PCICLK
FS3 FS2 FS1 FS0
CPU
SDRAM
Note: Please see full table on page 4.
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