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參數(shù)資料
| 型號： | ICS9248YF-189-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 236K |
| 代理商： | ICS9248YF-189-T |
Integrated
Circuit
Systems, Inc.
ICS9248-189
Third party brands and names are the property of their respective owners.
Block Diagram
9248-189 Rev - 08/10/01
Advance Information
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Functionality
Pin Configuration
48-Pin 300mil SSOP & 240mil TSSOP
Recommended Application:
VIA K7/KN/KX-133 style chipset
Output Features:
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
7 - SDRAM @ 3.3V
8 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support power management via hardware select CPU
stop, CLOCK stop, PCI stop, and SDRAM stop
Support power management via I
2C programing
Spread spectrum for EMI control
(± 0.25% to ± 0.06% center, or 0 to -0.5% or -1.0% down
spread)
Uses external 14.318MHz crystal
Key Specifications:
CPU - CPU Skew: <175ps
CPU - SDRAM Skew: ±125ps
CPU - PCI Skew: ±100ps
PCI - PCI Skew: <500ps
AMD - K7 Clock Generator for Mobile System
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1X or 1.5X strength
through I
2C
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
REF0
REF
REF2/FS3
GND
VDD
CPUCLK_CS
CPUCLKT0
CPUCLKC0
CPU_STOP#*
CLK_STOP#*/
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
1
2
1
*
PD#
ICS9248-189
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SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
CLK_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (5:0)
PCICLK (6:0)
PCICLK_F
SDRAM_F
CPUCLK_CS
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Control
Logic
Config.
Reg.
/ 2
REF (2:0)
SDRAM
DIVIDER
7
3
6
CPUCLKT0
CPUCLKC0
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Note: For a complete functionality table please see table in
page 3.
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