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參數(shù)資料
| 型號： | ICS9248YF-39-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 680K |
| 代理商： | ICS9248YF-39-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248-39
0277H—06/22/06
Block Diagram
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Pin Configuration
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
No external load cap for CL=18pF crystals
±175 ps CPU clock skew
250ps (cycle to cycle) CPU jitter
Smooth frequency switch, with selections from 66.8
to 150 MHz CPU.
I
2C interface for programming
3ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<5ns propagation delay SDRAM from Buffer Input
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK 1, CPUCLK_F
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
The ICS9248-39 generates all clocks required for high
speed RISC or CISC microprocessor systems such as
Intel
PentiumPro or Cyrix. Eight different reference
frequency multiplying factors are externally selectable
with smooth frequency transitions.
Features include two CPU, six PCI and thirteen SDRAM
clocks. Two reference outputs are available equal to the
crystal frequency. Plus the IOAPIC output powered by
VDDL1. One 48 MHz for USB, and one 24 MHz clock for
Super IO. Spread Spectrum built in at ±0.5% or ±0.25%
modulation to reduce the EMI. Serial programming I
2C
interface allows changing functions, stop clock programing
and Frequency selection. Additionally, the device meets
the Pentium power-up stabilization, which requires that
CPU and PCI clocks be stable within 2ms after power-up.
It is not recommended to use I/O dual function pin for the
slots (ISA, PIC, CPU, DIMM).The add on card might have
a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into
20pF loads while maintaining 50±5% duty cycle.The REF
and 24 and 48 MHz clock outputs typically provide better
than 0.5V/ns slew rates into 20pF.
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| ICS9248YF-72LF | 200.01 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9248YF-87LF | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YF-64 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7TM System Clock Chip |
| ICS9248YF-65 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENDIUM II Systems |
| ICS9248YF-66 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-72 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-73-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
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