參數(shù)資料
型號： ICS9248YF-87LF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 0.300 INCH, SSOP-48
文件頁數(shù)： 1/13頁
文件大小： 362K
代理商： ICS9248YF-87LF
Integrated
Circuit
Systems, Inc.
ICS9248-87
Third party brands and names are the property of their respective owners.
Block Diagram
9248-87 Rev D 10/27/00
Recommended Application:
810/810E type chipset.
Output Features:
2- CPUs @2.5V, up to 155MHz.
9 - SDRAM @ 3.3V, up to 155MHz.
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V
2- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V
1- REF @3.3V, 14.318MHz.
Features:
Up to 155MHz frequency support
Support FS0-FS3 strapping status bit for I
2C read back.
Support power management: Power down Mode from I
2C
programming.
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
Skew Specifications:
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
For group skew specification, please refer to group
timing relationships table.
Preliminary Product Preview
Functionality
Pin Configuration
48-Pin 300mil SSOP
*: These inputs have a 120K pull up to VDD.
1: These are double strength.
3
S
F2
S
F1
S
F0
S
F
U
P
C
)
z
H
M
(
/
U
P
C
M
A
R
D
S
M
A
R
D
S
)
z
H
M
(
6
V
3
)
z
H
M
(
K
L
C
I
C
P
*
6
V
3
(
)
2
/
1
)
z
H
M
(
C
I
P
A
O
I
*
I
C
P
(
)
2
/
1
)
z
H
M
(
C
I
P
A
O
I
)
I
C
P
(
)
z
H
M
(
00
3
.
3
80
0
.
13
.
3
88
4
.
5
54
7
.
7
27
8
.
3
14
7
.
7
2
00
0
1
0
.
4
2
10
0
.
10
0
.
4
2
17
6
.
2
83
3
.
1
47
6
.
0
23
3
.
1
4
00
1
0
.
5
10
0
.
10
0
.
5
13
3
.
3
0
17
6
.
1
53
8
.
5
27
6
.
1
5
00
11
6
9
.
3
4
13
3
.
10
0
.
8
0
10
0
.
2
70
0
.
6
30
0
.
8
10
0
.
6
3
01
0
.
0
77
6
.
00
0
.
5
0
10
0
.
0
70
0
.
5
30
5
.
7
10
0
.
5
3
01
0
.
2
1
10
0
.
10
0
.
2
1
17
6
.
4
73
3
.
7
37
6
.
8
13
3
.
7
3
01
1
0
.
0
5
10
0
.
10
0
.
0
5
10
0
.
0
10
0
.
0
50
0
.
5
20
0
.
0
5
01
1
0
.
0
4
13
3
.
10
0
.
5
0
10
0
.
0
70
0
.
5
30
5
.
7
10
0
.
5
3
10
0
3
.
8
67
6
.
00
5
.
2
0
13
3
.
8
67
1
.
4
38
0
.
7
17
1
.
4
3
10
0
1
0
.
7
0
10
0
.
10
0
.
7
0
13
3
.
1
77
6
.
5
33
8
.
7
17
6
.
5
3
10
0
.
8
3
10
0
.
10
0
.
8
3
10
0
.
2
90
0
.
6
40
0
.
3
20
0
.
6
4
10
1
3
.
7
3
13
3
.
10
0
.
3
0
17
6
.
8
64
3
.
4
37
1
.
7
14
3
.
4
3
11
00
0
8
.
6
67
6
.
00
2
.
0
10
8
.
6
60
4
.
3
30
7
.
6
10
4
.
3
11
0
1
0
3
.
0
10
0
.
10
3
.
0
10
8
.
6
60
4
.
3
30
7
.
6
10
4
.
3
11
1
0
6
.
3
10
0
.
10
6
.
3
17
0
.
9
83
5
.
4
47
2
.
2
23
5
.
4
11
0
6
.
3
13
3
.
10
2
.
0
10
8
.
6
60
4
.
3
30
7
.
6
10
4
.
3
Frequency Generator & Integrated Buffers for Celeron & PII/III
SEL24_48#
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK [1:0]
SDRAM [7:0]
SDRAM_F
IOAPIC
PCICLK [7:0]
8
2
8
2
3V66 [1:0]
X1
X2
XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
SDATA
SCLK
IC
2
FS[3:0]
PD#
Control
Logic
Config.
Reg.
/ 2
REF1
{
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
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