參數(shù)資料
型號(hào): ICS9248YF-175LF-T
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, SSOP-48
文件頁數(shù): 4/13頁
文件大?。?/td> 355K
代理商: ICS9248YF-175LF-T
12
ICS9248-175
Advance Information
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-175. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-175.
3. All other clocks continue to run undisturbed.
PCICLK
CPUCLKT
CPUCLKC0
PD# (High)
CPU_STOP#
INTERNAL
CPUCLK
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