IDT / ICS FREQUENCY GENERATOR/JITTER ATTENUATION
16
ICS813076CYI REV. A JULY 8, 2008
ICS813076I
FREQUENCY GENERATOR/JITTER ATTENUATION FOR WIRELESS INFRASTRUCTURE
SCHEMATIC LAYOUT
Figure 8 shows an example of the ICS813076I application
schematic. In this example, the device is operated at V
CC
= V
CCO
=
3.3V. The decoupling capacitors should be located as close as
possible to the power pin. The input is driven by a 3.3V LVPECL
VCC
(U1, 51)
VC
nQB0
R39
4.75K
Set Logic
Input to
'0'
R13
125
nSTOP
NB
1
Rs
0.64k
R3
820k
P
(U1, 54)
VCC
(U1, 46)
Cp
0.01uF
LVPECL Driv er
XT
AL
_
IN
Rs
0.64k
C30
0.1u
R13
125
VCCO
Logic Control Input Examples
QA0
TL1
Zo = 50 Ohm
C23
0.01u
Zo = 50
VCCO
R4
82.5
CLK1
Cs
10uF
VC
_
S
EL
C32
0.1u
NB
0
nQ
A
0
nMR
Zo = 50 Ohm
Zo = 50
nS
T
O
P
VCC
R2
133
VCCO
RD1
Not Install
(U1, 7)
(U1, 30)
MV
C22
SPARE
LF1
C3
220pF
3-pole loop filter example - (optional)
X1
30.72MHz, CL=10pF
LF 1
LF0
NC1
R7
50
R1
133
R12
84
nCLK1
VCC
3.3V
VCC
TL2
Zo = 50 Ohm
R4
82.5
QB2
VCC
C40
0.1u
+
-
R3
82.5
nQ
B
2
J30
Zo = 50 Ohm
(U1, 61)
LVPECL Termination
QB
2
RD2
1K
Optional
LVPECL
Y-Termination
3.3V
Zo = 50
MF
QB0
n
BY
PASS
R19
TBDk
C31
0.1u
LF0
C36
0.1u
FLM
R3
82.5
TL2
Zo = 50 Ohm
R11
125
To Logic
Input
pins
(U1, 15)
Set Logic
Input to
'1'
nCLK0
R6
50
R14
84
VCC
NA
0
CLK0
VCC
RU1
1K
C21
SPARE
C24
10u
+
-
(U1, 33)
R12
84
R11
125
ISET
(U1, 6)
NA1
R1
133
(U1, 37)
LOCK
QA
0
VCCO=3.3V
NC0
XT
AL
_
O
U
T
LVPECL Termination
R8
50
C33
0.1u
U1
ICS813076I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
39
38
37
36
35
34
33
32
31
30
29
28
27
52
51
50
49
48
47
46
45
44
43
42
41
40
53
54
55
56
57
58
59
60
61
62
63
64
LF1
LF0
ISET
VC
FLM
VCC
CLK1
nCLK1
nMR
CLK0
nCLK0
VEE
LOCK
VCCO
NA1
NA
0
NB
1
NB
0
NC1
NC0
P
n
BYPA
SS
nS
T
O
P
R
EF
_
SEL
nc
nQA4
QA4
VCC
VEE
nQB0
QB0
VCCO
nQ
B
1
QB
1
V
CCO
nQ
B
2
QB
2
V
CCA
nQ
C
0
VC
C
O
QA
0
nQ
A
0
nQA1
QA1
VCCO
nQA2
QA2
VEE
nQA3
QA3
VCCO
QC
0
VC
C
O
VE
E
nc
MF
MV
VC
_
SEL
VC
C
XT
A
L
_
O
U
T
XT
A
L
_
IN
VE
E
LF1
Cs
10uF
R2
133
nQB2
RU2
Not Install
VCC=3.3V
C38
0.1u
TL1
Zo = 50 Ohm
R37
10
(U1, 40)
+
-
LD1
C35
0.1u
R14
84
Zo = 50
nQB0
C40
0.1u
To Logic
Input
pins
C39
0.1u
LVPECL Driv er
nQA0
QB0
VCC
RE
F
_
S
E
L
Cp
0.01uF
VCCA
C37
0.1u
2-pole loop filter with Mid LBW Setting
driver. An optional 3-pole filter can also be used for additional
spur reduction. It is recommended that the loop filter components
be laid out for the 3-pole option. This will also allow the 2-pole
filter to be used.
FIGURE 8. ICS813076I APPLICATION SCHEMATIC