IDT / ICS FREQUENCY GENERATOR/JITTER ATTENUATION
12
ICS813076CYI REV. A JULY 8, 2008
ICS813076I
FREQUENCY GENERATOR/JITTER ATTENUATION FOR WIRELESS INFRASTRUCTURE
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS813076I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and 0.01F bypass capacitors should be used
for each pin.
Figure 3 illustrates this for a generic V
CC pin and also
shows that V
CCA requires
that an additional10
Ω resistor
along with a 10F bypass capacitor be connected to the V
CCA pin.
FIGURE 3. POWER SUPPLY FILTERING
10
Ω
V
CCA
10
μF
.01
μF
3.3V
.01
μF
V
CC
FIGURE 4. SINGLE-ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V
CC
= 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
V_REF
Single Ended Clock Input
VCC
CLKx
nCLKx
R1
1K
C1
0.1u
R2
1K