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| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
Preliminary
32Mx72 One Bank Registered DDR SDRAM Module
19L7358.H02502A
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 23
Electrical Characteristics and DC Operating Conditions
(0C
≤
T
A
≤
70
°
C; V
DDQ
= 2.5V
±
0.2V, V
DD
=
+
2.5V
±
0.2V, see AC Characteristics)
Symbol
Parameter
Min
Max
Units
Notes
V
DD
Supply Voltage
2.3
2.7
V
1
V
DDQ
I/O Supply Voltage
2.3
2.7
V
1
V
SS
, V
SSQ
Supply Voltage
I/O Supply Voltage
0
0
V
V
REF
I/O Reference Voltage
0.49
×
V
DDQ
0.51
×
V
DDQ
V
1, 2
V
TT
I/O Termination Voltage (System)
V
REF
0.04
V
REF
+
0.04
V
1, 3
V
DDSPD
Supply Voltage
SPD Supply Voltage
2.3
2.7
V
V
IH(DC)
Input High (Logic1) Voltage
DQ0-63,CB0-7,
DQS0-17
V
REF
+
0.15
V
DDQ
+
0.3
V
1
Address and
control inputs
V
REF
+
0.18
V
DDQ
+
0.3
RESET
1.7
V
DDQ
+
0.3
V
IL(DC)
Input Low (Logic0) Voltage
DQ0-63,CB0-7,
DQS0-17
0.3
V
REF
0.15
V
1
Address and
control inputs
0.3
V
REF
0.18
RESET
0.3
0.8
V
IN(DC)
Input Voltage Level, CK and CK Inputs
0.3
V
DDQ
+
0.3
V
1
V
ID(DC)
Input Differential Voltage, CK and CK Inputs
0.36
V
DDQ
+
0.6
V
1, 4
I
I
Input Leakage Current
Any input 0V
≤
V
≤
V
(All other pins not under test
=
0V)
Address and
control inputs
5
5
μ
A
1
DQ0-63,CB0-7,
DQS0-17
5
5
CK and CK
10
10
I
OZ
Output Leakage Current
(DQs are disabled; 0V
≤
V
OUT
≤
V
DDQ
DQ0-63,CB0-7,
DQS0-17
5
5
μ
A
1
SDA
1
1
I
OH
Output High Current
(V
OUT
=
1.95V)
16.8
mA
1
I
OL
Output Low Current
(V
OUT
=
0.35V)
16.8
mA
1
1. Inputs are not recognized as valid until V
REF
stabilizes.
2. V
REF
is expected to be equal to 0.5 V
DDQ
of the transmitting device, and to track variations in the DC level of the same. Peak-to-
peak noise on V
REF
may not exceed 2% of the DC value.
3. V
TT
is not applied directly to the DIMM. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
,
and must track variations in the DC level of V
REF
.
4. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
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