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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
32Mx72 One Bank Registered DDR SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 23
19L7358.H02502A
1/01
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
V
IN
, V
OUT
Voltage on I/O pins relative to V
SS
0.5 to V
DDQ
+
0.5
V
V
IN
Voltage on Inputs relative to V
SS
SDRAM
device
0.5 to
+
2.7
V
Serial PD
device
-0.3 to +6.5
V
V
DD
Voltage on V
DD
supply relative to V
SS
0.5 to
+
2.7
0.5 to
+
2.7
0.3 to +5.5
0 to
+
70
55 to
+
150
V
V
DDQ
Voltage on V
DDQ
supply relative to V
SS
V
V
DDSPD
Voltage on V
DDSPD
supply relative to V
SS
V
°
C
°
C
T
A
Operating Temperature (Ambient)
T
STG
Storage Temperature (Plastic)
P
D
Power Dissipation
TBD
W
I
OUT
Short Circuit Output Current
50
mA
Note:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter
Symbol
Max.
Units
Notes
Input Capacitance: CK0, CK0
C
I1
7
pF
1
Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS, CKE0, SO
C
I2
7
pF
1
Input Capacitance: RESET
C
I3
7
pF
1
Input Capacitance: SA0-SA2, SCL
C
I4
9
pF
1
Input/Output Capacitance: DQ0-63, DQS0-17, CB0-7
C
IO1
10
pF
1, 2
Input/Output Capacitance: SDA
C
IO2
11
pF
1. V
DDQ
= V
DD
= 2.5V 0.2V, f = 100 MHz, T
A
= 25
°
C, V
OUT
(DC) = V
DDQ/2
, V
OUT
(Peak to Peak) = 0.2V.
2. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching
at the board level.
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