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| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動(dòng)態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
32Mx72 One Bank Registered DDR SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 23
19L7358.H02502A
1/01
Electrical Characteristics and AC Timing - Absolute Specifications Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Character-
istics (Note 3) is V
TT
.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parame-
ters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or
begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for
this parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before
this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of
the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to
logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to
low at this time, depending on t
DQSS
.
8. A maximum of eight Auto-refresh commands can be posted to any given DDR SDRAM device.
9. QFC is enabled as soon as possible after the rising CK edge that registers the Write command.
10. QFC is disabled as soon as possible after the last valid DQS edge transitions Low.
11. For command/address input slew rate
≥
1.0V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
12. For command/address input slew rate
≥
0.5V/ns and < 1.0V/ns. Slew rate is measured between V
OH
(AC)
and V
OL
(AC).
13. CK/CK slew rates are
≥
1.0V/ns.
14. These parameters guarantee device timing, but they are not necessarily tested on each device, and they
may be guaranteed by design or tester characterization.
15. The specified timing is guaranteed assuming QFC is connected to a test load consisting of 20pF to
ground and a pull up resistor of 150 ohms to V
ddq
.
16. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t
CK
is
equal to the actual system clock cycle time.
(Notes continue on following page.)
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