參數(shù)資料
型號: IBMB6M32734HGA
廠商: IBM Microeletronics
英文描述: 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊)
中文描述: 32M的x72第一銀行注冊DDR SDRAM內存模塊(32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內存模塊)
文件頁數(shù): 16/23頁
文件大?。?/td> 421K
代理商: IBMB6M32734HGA
IBMB6M32734HGA
32Mx72 One Bank Registered DDR SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 23
19L7358.H02502A
1/01
Wiring and Topology
This section contains the information needed to understand the timing relationships presented in the AC
Characteristics section. Because the system designer must measure all signals at the first receiving device
(SDRAM DQ pin for data, register input pin for address and controls, and PLL check input pin for clock), the
following pages provide detailed information on these inputs. In some cases DIMM timing adjustments are
listed in the specifications, and in some cases it is recommended that the customer determine this informa-
tion via simulation. This section enables the customer to understand the device pinouts on the DIMM, the net
structures, and the loading associated with these devices. For detailed timing analysis, contact an IBM Mar-
keting Representative for simulation models. System-level modeling is strongly recommended to determine
delay adders of the entire net structure in the customer’s application.
Pin Assignments for the 256 Mbit DDR SDRAM Planar Component (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
24
25
43
42
26
27
28
29
41
40
39
38
30
31
32
33
37
36
35
34
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A10/AP
A0
A1
A2
A3
V
DD
A7
A6
A5
A4
V
SS
32M x 8 x 4 Bank
66-pin Plastic TSOP-II 400mil
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