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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
32Mx72 One Bank Registered DDR SDRAM Module
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 23
19L7358.H02502A
1/01
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V
SS
.
2. Tests for AC timing, I
DD
, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I
DD
tests may use a V
IL
to V
IH
swing of up to 1.5V in the test environment, but input timing is still ref-
erenced to V
REF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range
between V
IL(AC)
and V
IH(AC)
unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not
ring back above (below) the DC input LOW (HIGH) level.
AC Output Load Circuit Diagram
AC Operating Conditions
(0 C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V, See AC Characteristics)
Symbol
Parameter/Condition
Min
Max
Unit
Notes
V
IH(AC)
Input High (Logic 1) Voltage.
DQ0-63,CB0-7,
DQS0-17
V
REF
+ 0.31
V
1, 2
Address and
control inputs
V
REF
+ 0.35
V
IL(AC)
Input Low (Logic 0) Voltage.
DQ0-63,CB0-7,
DQS0-17
V
REF
0.31
V
1, 2
Address and
control inputs
V
REF
0.35
V
ID(AC)
Input Differential Voltage, CK and CK Inputs
0.7
V
DDQ
+ 0.6
V
1, 2, 3
V
IX(AC)
Input Differential Pair Cross Point Voltage, CK and CK Inputs
(0.5
×
V
DDQ
)
0.2
(0.5
×
V
DDQ
)
+
0.2
V
1, 2, 4
f
SSC
SSC modulation frequency
30
50
KHz
SSC
0
-.50
%
1. Input slew rate = 1V/ns
.
2. Inputs are not recognized as valid until V
REF
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V
IX
is expected to equal 0.5
×
V
DDQ
of the transmitting device and must track variations in the DC level of the same.
50
Timing Reference Point
Output
(V
OUT
)
30pF
V
TT
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