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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 11/23頁 |
| 文件大小： | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
Preliminary
32Mx72 One Bank Registered DDR SDRAM Module
19L7358.H02502A
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 23
Operating, Standby, and Refresh Currents
(0 C
≤
T
A
≤
70
°
C
;
V
DDQ
= 2.5V
±
0.2V; V
DD
= 2.5V
±
0.2V,
See AC Characteristics)
Symbol
Parameter/Condition
mA
Notes
I
DD0
Operating Current
: one logical bank; active / precharge; t
= t
; DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock
cycle
1418
1
I
DD1
Operating Current
: one bank; active / read / precharge; Burst = 2; t
= t
RC MIN
; CL = 2.5;
I
OUT
= 0mA; address and control inputs changing once per clock cycle
1553
1
I
DD2P
Precharge Power-Down Standby Current
: all banks idle; power-down mode; CKE
≤
V
IL MAX
878
1
I
DD2N
Idle Standby Current:
CS
≥
V
; all banks idle; CKE
≥
V
IH MIN
;
address and control inputs changing once per clock cycle
1013
1
I
DD3P
Active Power-Down Standby Current
: one bank active; power-down mode;
CKE
≤
V
IL MAX
878
1
I
DD3N
Active Standby Current
: one bank; active / precharge; CS
≥
V
;
CKE
≥
V
; t
= t
; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
1193
1
I
DD4R
Operating Current:
one bank; Burst = 2; reads; continuous burst; address and control inputs
changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL =
2.5; I
OUT
= 0mA
1913
1
I
DD4W
Operating Current
: one bank; Burst = 2; writes; continuous burst; address and control inputs
changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL = 2.5
1778
1
I
DD5
Auto-Refresh Current
:
t
RC
= t
RFC MIN
t
RC
= 7.8
μ
s
2183
1, 3
891
I
DD6
Self-Refresh Current
: CKE
≤
0.2V
43
1, 2
I
DD7
Operating current
: four bank; four bank interleaving with BL = 4, address and control inputs
randomly changing; 50% of data changing at every transfer; t
RC
= t
RC MIN
; I
OUT
= 0mA.
TBD
1
1. I
DD
specifications are valid after the SDRAMs are properly initialized.
2. Enables on-chip refresh and address counters.
3. Current at 7.8
μ
s is time averaged value of I
DD5
at t
RFC MIN
and I
DD2P
over 7.8
μ
s.
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