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參數(shù)資料
| 型號： | IBMB6M32734HGA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x72 One Bank Registered DDR SDRAM Module(32M x 72 1組寄存同步雙數(shù)據(jù)速率動態(tài)RAM模塊) |
| 中文描述： | 32M的x72第一銀行注冊DDR SDRAM內(nèi)存模塊（32M × 72配置一組寄存同步雙數(shù)據(jù)速率動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/23頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IBMB6M32734HGA |
IBMB6M32734HGA
Preliminary
32Mx72 One Bank Registered DDR SDRAM Module
19L7358.H02502A
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 23
Features
184-Pin Registered 8-Byte Dual In-Line Memory
Module
32Mx72 Double Data Rate (DDR) SDRAM
DIMM (32M
X
8 SDRAM
S
)
Performance:
Intended for 100 MHz applications
Inputs and outputs are SSTL-2 compatible
V
DD
= 2.5Volt
±
0.2, V
DDQ
= 2.5Volt
±
0.2
Single Pulsed RAS interface
SDRAMs have four internal banks for concur-
rent operation
Module has one physical bank
Bi-directional data strobe with one clock cycle
preamble and one-half clock post-amble
Differential clock inputs
Data is read or written on both clock edges
Address and control signals are fully synchro-
nous to positive clock edge
Programmable Operation:
- DIMM CAS Latency: 3, 3.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
Auto Refresh (CBR) and Self Refresh Modes
Automatic and controlled precharge commands
Power Down Mode
13/10/2 Addressing (row/column/bank)
7.8
μ
s Max. Average Periodic Refresh Interval
Card size: 5.25" x 0.157" x 1.70"
Gold contacts
SDRAM
S
in 66-pin TSOP-II Package
Serial Presence Detect
Description
IBMB6M32734HGA is a registered 184-Pin Double
Data Rate (DDR) Synchronous DRAM Dual In-Line
Memory Module (DIMM), organized as a one-bank
high-speed memory array. The 32Mx72 module is a
single-bank DIMM that uses nine 32Mx8 DDR
SDRAMs in 400 mil TSOP packages. This DIMM
achieves high-speed data transfer rates of up to 250
MHz.
The DIMM is intended for use in applications oper-
ating from 100 MHz to 125 MHz clock speeds with
data rates of 200 to 250 MHz. All control and
address signals are re-driven through registers to
the DDR SDRAM devices. The control and address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the
following rising clock edge.
A phase-locked loop (PLL) on the DIMM is used to
re-drive the differential clock signals to both the
DDR SDRAM devices and the registers, thus mini-
mizing system clock loading. Clock enable (CKE0)
controls all devices on the DIMM.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must
be programmed into the DIMM by address inputs
A0-A12 and I/O inputs BA0 and BA1 using the
mode register set cycle. The DIMM CAS latency
exceeds the SDRAM device specification by one
clock due to the address and control signals being
clocked to the SDRAM devices.
These DIMMs are manufactured using raw cards
developed for broad industry use by IBM as refer-
ence designs. The use of these common design
files will minimize electrical variation between sup-
pliers.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked during module assembly.
The last 128 bytes are available to the customer.
All IBM 184 DDR SDRAM DIMMs provide a high-
performance, flexible 8-byte interface in a 5.25” long
space-saving footprint.
PC1600
Units
DIMM CAS Latency
Clock Frequency
Clock Cycle
DQ Burst Frequency
3
3.5
125
8.0
250
f
CK
t
CK
f
DQ
100
10
200
MHz
ns
MHz
.
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