參數(shù)資料
型號： IBM25EMPPC750EBUB2660
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù)： 43/43頁
文件大?。?/td> 431K
代理商： IBM25EMPPC750EBUB2660
Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
9 of 43
4. Full-on mode uses a worst case instruction mix.
5. Guaranteed by design and characterization, and is not tested.
6. Guaranteed and tested in Low Power Applications only, see Section 8.0, “Ordering Information“
3.1.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the PPC740 and PPC750.
After fabrication, parts are sorted by maximum processor core frequency as shown in
Section 3.1.2.1, “Clock AC Specications“ and tested for conformance to the AC speci-
cations for that frequency. These specications are for 166, 200, 225, 233, and 266
MHz processor core frequencies. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals. Parts are sold by
maximum processor core frequency; see Section 1.9, "Ordering Information".
3.1.2.1 Clock AC Specications
Table 7 provides the clock AC timing specications as dened in Figure 2 .
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0-3] settings must be chosen such that the result-
ing SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description
in Section 7.1, “PLL Conguration“ for valid PLL_CFG[0-3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during
the power-on reset sequence. This specication also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a min-
imum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
*
Subject to availability - see your marketing representative.
Table 7. Clock AC Timing Specications
Operating conditions are specied in Section Table 2., "Recommended Operating Conditions"
Nu
m
Characteristic
166/200 MHz
225/233 MHz
266 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Processor frequency
150
200
150
233
150
266
MHz
VCO frequency
300
400
300
466
300
533
MHz
SYSCLK frequency
25
100
25
100
25
100
MHz
1
SYSCLK cycle time
12
40
12
40
12
40
ns
2,3
SYSCLK rise and fall time
—
2.0
—
2.0
—
2.0
ns
2,3
4
SYSCLK duty cycle mea-
sured at 1.4 V
40
60
40
60
40
60
%
3
SYSCLK jitter
—
±150
—
±150
—
±150
ps
4,3
Internal PLL relock time
—
100
—
100
—
100
s5
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