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參數(shù)資料
| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（4M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）) |
| 中文描述： | 4米× 72注冊內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（4米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 8/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 56
08J0512.E24526
Released 4/98
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with S0 and RAS low at the rising edge
of the clock. The bank select address, A11/BS is used to select the desired bank. If BS is low then bank A is
activated, if BS is high then bank B is activated. Row address A0 - A10 selects the active row in the selected
bank.
The Bank Activate command must be applied before any Read or Write operation can be executed. The
delay from when the Bank Activate command is applied to when the first Read or Write operation can begin
must meet or exceed the RAS to CAS delay time (t
RCD
or 30ns). Once a bank has been activated it must be
precharged before another Bank Activate command can be applied to the same bank. The minimum time
interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time
of the device (t
RC
). The minimum time interval between interleaved Bank Activate commands (Bank A to
Bank B and vice versa) is the Bank to Bank delay time (t
RRD
).
Bank Activate Command Timing
(CAS Latency = 2)
ADDRESS
CK0
T0
T2
T1
Tn
Tn+1
Tn+2
COMMAND
NOP
NOP
Bank A
Row Addr.
Bank A
Activate
Write A
with Auto
Bank A
Col. Addr.
Bank B
Activate
Bank A
Row Addr.
Bank A
Activate
RAS-CAS delay (
t
RCD
)
: “H” or “L”
RAS Cycle time (
t
RC
)
RAS - RAS delay time (
t
RRD
)
Bank B
Row Addr.
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
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