參數(shù)資料
型號(hào)： IBM13Q4739CC
廠商： IBM Microeletronics
英文描述： 4M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（4M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 4米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（4米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁(yè)數(shù)： 22/56頁(yè)
文件大?。?/td> 1471K
代理商： IBM13Q4739CC
IBM13Q4739CC
4M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 22 of 56
08J0512.E24526
Released 4/98
Write
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
Terminate Burst; Start the Precharge
L
L
H
H
BS
Row Address Bank Activate
ILLEGAL
3
L
H
L
L
BS
Column
Write
Terminate Burst; Start a new Write cycle
7, 8
L
H
L
H
BS
Column
Read
Terminate Burst; Start the Read cycle
7, 8
L
H
H
L
X
X
Burst Termination
Terminate the Burst
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Read with
Auto
Precharge
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
3
L
L
H
H
BS
Row Address Bank Activate
ILLEGAL
3
L
H
L
L
BS
Column
Write
ILLEGAL
L
H
L
H
BS
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Write with
Auto
Precharge
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
3
L
L
H
H
BS
Row Address Bank Activate
ILLEGAL
3
L
H
L
L
BS
Column
Write
ILLEGAL
L
H
L
H
BS
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Current State Truth Table
(
CKE0 is assumed to be active (high) in the previous cycle for all entries. The Current State is
the state of the bank that the command is being applied to.
)
Current
State
Command
Action
Notes
S0
RAS CAS WE
A11/BS
A10/AP - A0
Description
1. Both Banks must be idle otherwise it is an illegal action.
2. If CKE0 is active (high) the SDRAM DIMM starts the Auto (CBR) Refresh operation, if CKE0 is inactive (low) than the Self Refresh
mode is entered.
3. The Current State refers only refers to one of the banks, if BS selects this bank then the action is illegal. If BS selects the bank not
being referenced by the Current State then the action may be legal depending on the state of that bank.
4. If CKE0 is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.
5. The minimum and maximum Active time (t
RAS
) must be satisfied.
6. The RAS to CAS Delay (t
RCD
) must occur before the command is given.
7. Column address A10 is used to determine if the Auto Precharge function is activated.
8. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
9. The command is illegal if the minimum bank to bank delay time (t
RRD
) is not satisfied.
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