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參數(shù)資料
| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（4M x 72高速存儲器陣列結(jié)構(gòu)）) |
| 中文描述： | 4米× 72注冊內(nèi)存模塊（帶寄存同步動態(tài)內(nèi)存模塊（4米× 72高速存儲器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 56
Write Interrupted by a Read
A Read command will interrupt a Burst Write operation on the next clock cycle after the Read command is
registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read command is registered, any residual data
from the Burst Write cycle will be ignored. Data that is presented on the DQ pins before the Read command
is initiated will actually be written to the memory.
Write Interrupted by a Read
(Burst Length = 2, CAS Latency = 2)
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
DIN A0
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
don’t care
DOUT B0
DOUT B1
NOTE: Data is delayed one cycle due to on-DIMM pipeline register
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