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參數資料
| 型號： | IBM13Q4739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（4M x 72高速存儲器陣列結構）) |
| 中文描述： | 4米× 72注冊內存模塊（帶寄存同步動態(tài)內存模塊（4米× 72高速存儲器陣列結構）） |
| 文件頁數： | 3/56頁 |
| 文件大?。?/td> | 1471K |
| 代理商： | IBM13Q4739CC |
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IBM13Q4739CC
4M x 72 Registered SDRAM Module
08J0512.E24526
Released 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 56
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Positive
Edge
Function
CK0
Input
Pulse
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE0
Input
Level
Active
High
Activates the CK0 signal when high and deactivates the CK0 signal when low. By deacti-
vating the clock, CKE0 low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
S0 enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
S0
Input
Pulse
Active Low
RAS, CAS
WE
A11/BS
Input
Pulse
Active Lowoperation to be executed by the SDRAM.
Input
Level
—
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A10/AP defines the row address (RA0-
RA10) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10/AP is
used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If
A10/AP is high, autoprecharge is selected and A11/BS defines the bank to be pre-
charged (low=bank A, high=bank B). If A10/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with A11/BS to con-
trol which bank(s) to precharge. If A10/AP is high, both bank A and bank B will be pre-
charged regardless of the state of A11/BS. If A10/AP is low, then A11/BS is used to
define which bank to precharge.
A0 - A9,
A10/AP
A11/BS
Input
Level
—
DQ0 - DQ71
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAM DIMMs.
DQM
Input
Pulse
Mask
Active
High
The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of three clock cycles and controls the out-
put buffers like an output enable. In Write mode, DQM has a latency of one and operates
as a word mask by allowing input data to be written if it is low but blocks the Write opera-
tion if DQM is high.
VDD, VSS
Supply
Power and ground for the input buffers and the core logic.
Presence Detect
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID1
ID2
ID3
Value
0
1
0
1
1
0
1
1
1
0
0
Notes
1
1
1
1
1
1
1
1
2
2
2
1. 0 = driven to V
OL
, 1 = open
2. 0 = ground, 1 = open
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