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參數(shù)資料
| 型號(hào)： | IBM13M64734CCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 2-Bank Registered/Buffered SDRAM Module(64M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 64米× 72 2，銀行注冊(cè)/緩沖內(nèi)存模組（64米× 72 2組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 867K |
| 代理商： | IBM13M64734CCA |
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IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 20
09K3884.F38744
10/99
29
Minimum RAS to CAS delay (t
RCD
)
20.0ns
14
30
Minimum RAS Pulse width (t
RAS
)
50.0ns
32
31
Module Bank Density
256MB
40
32
Address and Command Setup Time Before Clock
2.0ns
20
33
Address and Command Hold Time After Clock
1.0ns
10
34
Data Input Setup Time Before Clock
2.0ns
20
35
Data Input Hold Time After Clock
1.0ns
10
36 - 61
Reserved
Undefined
00
62
SPD Revision
PC100 1.2A
12
63
Checksum for bytes 0 - 62
Checksum Data
cc
3
64 - 71
Manufacturers’ JEDEC ID Code
IBM
A400000000000000
72
Assembly Manufacturing Location
Toronto, Canada
91
Vimercate, Italy
53
73 - 90
Assembly Part Number
-260
ASCII ‘13M64734CC”R”-
260Y’
31334D36343733344343rr
2D323630592020
4, 5
-360
ASCII ‘13M64734CC”R”-
360Y’
31334D36343733344343rr
2D333630592020
91 - 92
Assembly Revision Code
“R” plus ASCII blank
rr20
5
93 - 94
Assembly Manufacturing Date
Year/Week Code
yyww
6, 7
95 - 98
Assembly Serial Number
Serial Number
ssssssss
8
99 - 125 Reserved
Undefined
Not Specified
126
Module Supports this Clock Frequency
100MHz
64
127
Attributes for clock frequency defined in
Byte 126
-260
CLK0, CL=2,3 ConAP
87
-360
CLK0, CL=3, ConAP
85
128 - 255 Open for Customer Use
Undefined
00
Serial Presence Detect (Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
Notes
1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (i.e., Device CL [clock cycles]
+ 1 = DIMM CAS latency).
2. Minimum application clock cycle time is 10ns (100MHz) for the -260 and -360.
3. cc = Checksum Data byte, 00-FF (Hex).
4. “R” = Alphanumeric revision code, A-Z, 0-9.
5. rr = ASCII coded revision code byte “R”.
6. ww = Binary coded decimal week code, 01-52 (Decimal)
01-34 (Hex).
7. yy = Binary coded decimal year code, 00-99 (Decimal)
00-63 (Hex).
8. ss = Serial number data byte, 00-FF (Hex).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM13M64734HCA | 64M x 72 Two-Bank Registered SDRAM Module(64M x 72 2組帶寄存同步動(dòng)態(tài)RAM模塊) |
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| IBM13M8734HCC | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
| IBM13M8734HCD | 8M x 72 1 Bank Registered/Buffered SDRAM Module(8M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊) |
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