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參數(shù)資料
| 型號： | IBM13M64734CCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 64M x 72 2-Bank Registered/Buffered SDRAM Module(64M x 72 2組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 64米× 72 2，銀行注冊/緩沖內(nèi)存模組（64米× 72 2組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 867K |
| 代理商： | IBM13M64734CCA |
IBM13M64734CCA
64M x 72 2-Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 20
09K3884.F38744
10/99
Read Cycle
Symbol
Parameter
-260
-360
Units
Notes
Min.
Max.
Min.
Max.
t
OH
t
LZ
t
HZ3
t
HZ2
Data Out Hold Time
3.6
3.6
ns
Data Out to Low Impedance Time
0.6
0.6
ns
Data Out to High Impedance Time
3.5
6.7
3.5
6.7
ns
1
Data Out to High Impedance Time
3.5
6.7
3.5
6.7
ns
t
DQZ
DQM Data Out Disable Latency
Registered
Buffered
3
2
3
2
CLK
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Write Cycle
Symbol
Parameter
-260
-360
Units
Min.
Max.
Min.
Max.
t
DS
Data In Setup Time
2.1
—
2.1
—
ns
t
DH
Data In Hold Time
1.6
—
1.6
—
ns
t
DPL
Data input to Precharge
Registered
10
—
10
—
ns
Buffered
20
—
20
—
ns
t
DAL3
Data input to Active, CL = 3
Registered
4
—
4
—
CLK
Buffered
5
—
5
—
CLK
t
DAL2
Data input to Active CL = 2
Registered
4
—
4
—
CLK
Buffered
5
—
5
—
CLK
t
DQW
DQM Write Mask Latency
Registered
1
—
1
—
CLK
Buffered
0
—
0
—
CLK
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