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參數(shù)資料
| 型號： | IBM043614PQKB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32K X 36 BURST SRAM(1M (32K X 36)同步可猝發(fā)高性能靜態(tài)RAM) |
| 中文描述： | 32KX8的36爆的SRAM（100萬（32KX8的36）同步可猝發(fā)高性能靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 7/13頁 |
| 文件大小： | 219K |
| 代理商： | IBM043614PQKB |
IBM043614PQKB
32K X 36 BURST SRAM
8190747
SA14-4652-03
Revised 9/97
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 13
AC Characteristics
(T
A
=0 to +70
°
C, V
DD
=3.3V
±
5%, Units in nsec)
Parameter
Symbol
-8
-9
-10
-11
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Cycle Time
t
CYCLE
15.0
—
15.0
—
15.0
—
15.0
—
Clock Pulse High
t
CH
3.0
—
3.0
—
3.0
—
3.0
—
Clock Pulse Low
t
CL
3.0
—
3.0
—
3.0
—
3.0
—
Clock to Output Valid
t
CQ
—
8.0
—
9.0
—
10.0
—
11.0
3
Address Status Controller Setup Time
t
ADSCS
2.5
—
2.5
—
2.5
—
2.5
—
Address Status Controller Hold Time
t
ADSCH
0.5
—
0.5
—
0.5
—
0.5
—
Address Status Processor Setup Time
t
ADSPS
2.5
—
2.5
—
2.5
—
2.5
—
Address Status Processor Hold Time
t
ADSPH
0.5
—
0.5
—
0.5
—
0.5
—
Advance Setup Time
t
ADVS
2.5
—
2.5
—
2.5
—
2.5
—
Advance Hold Time
t
ADVH
0.5
—
0.5
—
0.5
—
0.5
—
Address Setup Time
t
AS
2.5
—
2.5
—
2.5
—
2.5
—
Address Hold Time
t
AH
0.5
—
0.5
—
0.5
—
0.5
—
Chip Selects Setup Time
t
CSS
2.5
—
2.5
—
2.5
—
2.5
—
Chip Selects Hold Time
t
CSH
0.5
—
0.5
—
0.5
—
0.5
—
Write Enables Setup Time
t
WES
2.5
—
2.5
—
2.5
—
2.5
—
Write Enables Hold Time
t
WEH
0.5
—
0.5
—
0.5
—
0.5
—
Data In Setup Time
t
DS
2.5
—
2.5
—
2.5
—
2.5
—
Data In Hold Time
t
DH
0.5
—
0.5
—
0.5
—
0.5
—
Data Out Hold Time
t
CQX
3.0
—
3.0
—
3.0
—
3.0
—
3
Clock High to Output High-Z
t
CHZ
—
5.0
—
5.0
—
5.5
—
5.5
1, 2, 4
Clock High to Output Active
t
CLZ
2.5
—
2.5
—
2.5
—
2.5
—
1, 2, 4
Output Enable to High-Z
t
OHZ
2.0
5.0
2.0
5.5
2.0
6.0
2.0
6.5
1, 4
Output Enable to Low-Z
t
OLZ
0.25
—
0.25
—
0.25
—
0.25
—
1, 4
Output Enable to Output Valid
t
OQ
—
4.0
—
5.0
—
5.0
—
6.0
3
1. Transitions are measured
±
200 mV from steady state voltage.
2. At any given voltage and temperature, T
CHZ
(max) is always less than T
CLZ
(min) for a given device and from device to device. For
any read cycle preceded by a write or deselect cycle, the data bus will transition glitch-free from High-Z to new RAM data.
3. See AC Test Loading figure 1 on page 8.
4. See AC Test Loading figure 2 on page 8.
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