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參數(shù)資料
| 型號： | HYE18M256320CF-7.5 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 6 ns, PBGA90 |
| 封裝： | 10 X 12.50 MM, 1 MM HEIGHT, GREEN, VFBGA-90 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | HYE18M256320CF-7.5 |
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Internet Data Sheet
Rev.1.44, 2007-07
17
06262007-JK8G-48BV
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
Read preamble
CL = 3
t
RPRE
0.9
1.1
0.9
1.1
t
CK
20)
CL = 2
–
0.5
1.1
Read postamble
t
RPST
0.4
0.6
0.4
0.6
t
CK
–
ACTIVE to PRECHARGE command period
t
RAS
42
70k
45
70k
ns
21)
ACTIVE to ACTIVE command period
t
RC
60
–
67
–
ns
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
t
RFC
72
–
75
–
ns
ACTIVE to READ or WRITE delay
t
RCD
18
–
22.5
–
ns
Col address to col address delay
t
CCD
1–
1
–
t
CK
PRECHARGE command period
t
RP
18
–
22.5
–
ns
ACTIVE bank A to ACTIVE bank B delay
t
RRD
12
–
15
–
ns
WRITE recovery time
t
WR
15
–
15
–
ns
Auto precharge write recovery + precharge time
t
DAL
(t
WR/tCK) + (tRP/tCK)
t
CK
22)
Internal write to Read command delay
t
WTR
1–
1
–
t
CK
23)
Self refresh exit to next valid command delay
t
XSR
120
–
120
–
ns
Exit power down delay
t
XP
t
CK + tIS
–
t
CK + tIS
–ns
–
CKE minimum low time
t
CKE
2–
2
–
t
CK
–
Refresh period
t
REF
–64
–
64
ms
Average periodic refresh interval
t
REFI
–
7.8 (× 16)
15.6 (x32)
–
7.8 (× 16)
15.6 (x32)
s
24)
1) 0
°C ≤ T
C ≤ 70 °C (comm.); -25°C ≤ TC ≤ 85 °C (ext.);VDD = 1.70 V - 1.95 V, VDDQ = 1.70 V - 1.95 V. All voltages referenced to VSS.
2) All parameters assume proper device initialization.
3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK; the input reference level for signals
other than CK/CK is
V
DDQ/2.
4) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
5) The output timing reference level is
V
DDQ/2.
6) Parameters
t
AC and tQH are specified for full drive strength and a reference load see Figure 3. This circuit is not intended to be either a
precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive
strength with a nominal load of 10pF parameters
t
AC and tQH are expected to be in the same range. However, these parameters are not
subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is
suggested.
7) Min (
t
CL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for
t
CL and tCH).
8)
t
QH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
9) DQ, DM and DQS input slew rate is measured between
V
ILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
11) Input slew rate
≥ 1.0 V/ns.
12) Input slew rate
≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between
V
IH and VIL.
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16)
t
HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Parameter
Symbol
– 6
– 7.5
Unit Note
1)2)3)4)
Min.
Max.
Min.
Max.
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