參數(shù)資料
型號(hào)： HYE18M256320CF-7.5
廠(chǎng)商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 8M X 32 DDR DRAM, 6 ns, PBGA90
封裝： 10 X 12.50 MM, 1 MM HEIGHT, GREEN, VFBGA-90
文件頁(yè)數(shù)： 11/26頁(yè)
文件大?。?/td> 1609K
代理商： HYE18M256320CF-7.5
Internet Data Sheet
Rev.1.44, 2007-07
19
06262007-JK8G-48BV
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
3.3
Operating Currents
TABLE 13
Maximum Operating Currents
Parameter & Test Conditions
Symbol
Values
Unit
Note
1)2)3)4)5)
– 6
– 7.5
Operating one bank active-precharge current:
t
RC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are
STABLE
I
DD0
45 (x16)
60 (x32)
40 (x16)
55 (x32)
mA
Precharge power-down standby current:
All banks idle, CKE is LOW; CS is HIGH,
t
CK = tCKmin; address and control
inputs are SWITCHING; data bus inputs are STABLE
I
DD2P
0.7
mA
Precharge power-down standby current with clock stop:
All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address
and control inputs are SWITCHING; data bus inputs are STABLE
I
DD2PS
0.3
mA
Precharge non power-down standby current:
All banks idle, CKE is HIGH; CS is HIGH,
t
CK = tCKmin;address and control
inputs are SWITCHING; data bus inputs are STABLE
I
DD2N
15
mA
Precharge non power-down standby current with clock stop:
All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;address
and control inputs are SWITCHING; data bus inputs are STABLE
I
DD2NS
88
mA
Active power-down standby current:
One bank active, CKE is LOW; CS is HIGH,
t
CK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
I
DD3P
2.0
mA
Active power-down standby current with clock stop:
One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
I
DD3PS
1.5
mA
Active non power-down standby current:
One bank active, CKE is HIGH; CS is HIGH,
t
CK = tCKmin;address and
control inputs are SWITCHING; data bus inputs are STABLE
I
DD3N
25
23
mA
Active non power-down standby current with clock stop:
One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK =
HIGH;address and control inputs are SWITCHING; data bus inputs are
STABLE
I
DD3NS
20
mA
Operating burst read current:
One bank active; BL = 4; CL = 3;
t
CK = tCKmin; continuous read bursts; IOUT
= 0 mAaddress inputs are SWITCHING; 50% data change each burst
transfer
I
DD4R
115 (x16)
140 (x32)
90 (x16)
110 (x32)
mA
Operating burst write current:
One bank active; BL = 4;
t
CK = tCKmin; continuous write bursts; address
inputs are SWITCHING; 50% data change each burst transfer
I
DD4W
110 (x16)
115 (x32)
85 (x16)
90 (x32)
mA
Auto-Refresh current:
t
RC = tRFCmin; tCK = tCKmin; burst refresh; address and control inputs are
SWITCHING; data bus inputs are STABLE
I
DD5
75 (x16)
120 (x32)
70 (x16)
110 (x32)
mA
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