參數(shù)資料
型號: HYB25D256160TG-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 122 x 32 pixel format, LED Backlight available
中文描述: 記憶譜
文件頁數(shù): 66/94頁
文件大小: 3326K
代理商: HYB25D256160TG-3
Data Sheet
69
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
Table 20
AC Operating Conditions1)
Parameter
Symbol
Values
Unit Note/
Test
Condition
Min.
Max.
Input High (Logic 1) Voltage, DQ, DQS and DM Signals
VIH(AC) VREF + 0.31 —
V
2)3)
Input Low (Logic 0) Voltage, DQ, DQS and DM Signals
VIL(AC)
VREF – 0.31 V
Input Differential Voltage, CK and CK Inputs
VID(AC) 0.7
VDDQ + 0.6 V
Input Closing Point Voltage, CK and CK Inputs
VIX(AC) 0.5 × VDDQ
– 0.2
0.5
× VDDQ
+ 0.2
V
1)
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);
0
°C ≤ TA ≤ 70 °C
2) Input slew rate = 1 V/ns.
3) Inputs are not recognized as valid until
VREF stabilizes.
4)
VID is the magnitude of the difference between the input level on CK and the input level on CK.
5) The value of
VIX is expected to equal 0.5 × VDDQ of the transmitting device and must track variations in the DC level of the
same.
Table 21
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note/ Test
Condition 1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
DQ output access time from
CK/CK
tAC
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK 2)3)4)5)
Clock cycle time
tCK
5
8
6
12
ns
CL = 3.0
2)3)4)5)
6
12
6
12
ns
CL = 2.5
2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK 2)3)4)5)
Auto precharge write recovery
+ precharge time
tDAL
(
tWR/tCK)+(tRP/tCK)
tCK 2)3)4)5)6)
DQ and DM input hold time
tDH
0.4
0.45
ns
2)3)4)5)
DQ and DM input pulse width
(each input)
tDIPW
1.75
1.75
ns
2)3)4)5)6)
DQS output access time from
CK/CK
tDQSCK –0.6
+0.6
–0.6
+0.6
ns
2)3)4)5)
DQS input low (high) pulse
width (write cycle)
tDQSL,H 0.35
0.35
tCK 2)3)4)5)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
+0.40
+0.40
ns
TFBGA
2)3)4)5)
+0.40
+0.45
ns
TSOPII
2)3)4)5)
Write command to 1st DQS
latching transition
tDQSS
0.72
1.25
0.75
1.25
tCK 2)3)4)5)
DQ and DM input setup time
tDS
0.4
0.45
ns
2)3)4)5)
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