參數資料
型號: HYB25D256160TG-3
廠商: INFINEON TECHNOLOGIES AG
英文描述: 122 x 32 pixel format, LED Backlight available
中文描述: 記憶譜
文件頁數: 52/94頁
文件大?。?/td> 3326K
代理商: HYB25D256160TG-3
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Data Sheet
56
Rev. 1.6, 2004-12
3.5.5
Power-Down
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input
and output buffers, excluding CK, CK and CKE. The DLL is still running in Power Down mode, so for maximum
power savings, the user has the option of disabling the DLL prior to entering Power-down. In that case, the DLL
must be enabled after exiting power-down, and 200 clock cycles must occur before a Read command can be
issued. In power-down mode, CKE Low and a stable clock signal must be maintained at the inputs of the
DDR SDRAM, and all other input signals are “Don’t Care”. However, power-down duration is limited by the refresh
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled
power-down mode.
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect
command). A valid, executable command may be applied one clock cycle later.
Figure 31
Power Down
tIS
CK
CKE
Command
No column
access in
progress
VALID
NOP
VALID
Don’t Care
Exit
power down
mode
Enter Power Down mode
(Burst Read or Write operation
must not be in progress)
NOP
相關PDF資料
PDF描述
HYB39T256160TG-3 122 x 32 pixel format, LED Backlight available
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