參數(shù)資料
型號： HYB25D256160CC-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbit Double Data Rate SDRAM
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù)： 72/94頁
文件大?。?/td> 3326K
代理商： HYB25D256160CC-5
Data Sheet
74
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
Table 23
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge;
tRC = tRCMIN; tCK = tCKMIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once
every two clock cycles.
IDD0
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
IDD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE
≤ VILMAX; tCK =
tCKMIN
IDD2P
Precharge Floating Standby Current: CS
≥ VIHMIN, all banks idle;
CKE
≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF
for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current:
CS
≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs stable
at
≥ VIHMIN or ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD2Q
Active Power-Down Standby Current: one bank active; power-down mode;
CKE
≤ VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS
≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN;
DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per
clock cycle.
IDD3N
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
tCK = tCKMIN; IOUT =0 mA
IDD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
tCK = tCKMIN
IDD4W
Auto-Refresh Current:
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current: CKE
≤ 0.2 V; external clock on; tCK = tCKMIN
IDD6
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for
detailed test conditions.
IDD7
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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