參數(shù)資料
型號: HYB25D256160CC-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 Mbit Double Data Rate SDRAM
中文描述: 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 43/94頁
文件大?。?/td> 3326K
代理商: HYB25D256160CC-5
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Data Sheet
48
Rev. 1.6, 2004-12
Figure 23
Write to Read: Interrupting (CAS Latency = 2; Burst Length = 8)
T1
T2
T3
T4
T5
T6
tDQSS (max)
Maximum DQSS
NOP
Read
Write
NOP
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 4 data elements are written.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
tWTR is referenced from the first positive CK edge after the last data in pair.
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
DIa- b
CK
Command
Address
DQS
DQ
DM
Don’t Care
BAa, COL b
BAa, COL n
tWTR
CL = 2
T1
T2
T3
T4
T5
T6
Minimum DQSS
NOP
Read
Write
NOP
CK
Command
Address
BAa, COL b
BAa, COL n
tWTR
DI a-b
DQS
DQ
DM
CL = 2
tDQSS (min)
1 = These bits are incorrectly written into the memory array if DM is low.
11
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