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參數(shù)資料
| 型號： | HYB25D256160CC-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbit Double Data Rate SDRAM |
| 中文描述： | 256兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 17/94頁 |
| 文件大?。?/td> | 3326K |
| 代理商： | HYB25D256160CC-5 |
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HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Data Sheet
24
Rev. 1.6, 2004-12
3.2.1
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst
length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both Read and Write bursts.
3.2.2
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 7.
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
Table 7
Burst Definition
Burst
Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
20
0-1
11-0
1-0
4
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
0000-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0011-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0102-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0113-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1004-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1015-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1106-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1117-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25S256160AC-7.5 | 16M X 16 SYNCHRONOUS DRAM, 7.5 ns, PBGA54 |
| HYB39S128160TEL-37 | MEMORY SPECTRUM |
| HYB39S128160TEL-5 | MEMORY SPECTRUM |
| HYB39S128160TEL-7 | MEMORY SPECTRUM |
| HYB39S128160TEL-75 | MEMORY SPECTRUM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D256160CC-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256 Mbit Double Data Rate SDRAM |
| HYB25D256160CE-5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
| HYB25D256160CE-5A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
| HYB25D256160CE-6 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
| HYB25D256160CEL-6 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:256-Mbit Double-Data-Rate SDRAM |
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