參數(shù)資料
型號： HYB25D256160CC-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbit Double Data Rate SDRAM
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù)： 60/94頁
文件大小： 3326K
代理商： HYB25D256160CC-5
Data Sheet
63
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
Table 16
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note/Test Condition 1)
1) 0
°C ≤ TA ≤ 70 °C
Min.
Typ.
Max.
Device Supply Voltage
VDD
2.3
2.5
2.7
V
fCK ≤ 166 MHz
Device Supply Voltage
VDD
2.5
2.6
2.7
V
fCK >166 MHz 2)
2) DDR400 conditions apply for all clock frequencies above 166 MHz
Output Supply Voltage
VDDQ
2.3
2.5
2.7
V
fCK ≤ 166 MHz 3)
3) Under all conditions,
VDDQ must be less than or equal to VDD.
Output Supply Voltage
VDDQ
2.5
2.6
2.7
V
fCK >166 MHz 2)3)
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
00
V
—
Input Reference Voltage
VREF
0.49
×
VDDQ
0.5
×
VDDQ
0.51
×
VDDQ
V
4)
4) Peak to peak AC noise on
VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
I/O Termination Voltage
(System)
VTT
VREF – 0.04
VREF + 0.04 V
5)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to
VREF, and must track variations in the DC level of VREF.
Input High (Logic1) Voltage
VIH(DC) VREF + 0.15
VDDQ + 0.3 V
8)
Input Low (Logic0) Voltage
VIL(DC) –0.3
VREF – 0.15 V
8)
Input Voltage Level,
CK and CK Inputs
VIN(DC) –0.3
VDDQ + 0.3 V
8)
Input Differential Voltage,
CK and CK Inputs
VID(DC) 0.36
VDDQ + 0.6 V
8)6)
6)
VID is the magnitude of the difference between the input level on CK and the input level on CK.
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio
0.71
1.4
—
7)
7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
Input Leakage Current
II
–2
2
A
Any input 0 V
≤ VIN ≤ VDD;
All other pins not under test
=0V 8)9)
8) Inputs are not recognized as valid until
VREF stabilizes.
9) Values are shown per component
Output Leakage Current
IOZ
–5
5
A
DQs are disabled;
0V
≤ VOUT ≤ VDDQ
Output High Current,
Normal Strength Driver
IOH
—
–16.2
mA
VOUT = 1.95 V
Output Low
Current, Normal Strength
Driver
IOL
16.2
—
mA
VOUT = 0.35 V
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