參數(shù)資料
型號(hào): HYB25D128400ATL-8
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù): 7/79頁(yè)
文件大?。?/td> 2596K
代理商: HYB25D128400ATL-8
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Overview
Data Sheet
7
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
coincident with the Active command are used to select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are used to select the bank and the starting column location
for the burst access.
The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto
Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
Note:The functionality described and the timing specifications included in this data sheet are for the DLL Enabled
mode of operation.
Table 2
Type
Ordering Information
1)
1) Low Power Versions have a “L” in the partnumber, for example HYB25D128400ATL-8. These components are specifically
selected for low IDD6 Self Refresh currents.
CAS
Latency
2.5
Clock
(MHz)
125
CAS
Latency
2
Clock
(MHz)
100
Speed
Org.
Package
HYB25D128400AT(L)-8
HYB25D128800AT(L)-8
HYB25D128160AT(L)-8
HYB25D128400AT(L)-7
HYB25D128800AT(L)-7
HYB25D128160AT(L)-7
HYB25D128400AT(L)-6
HYB25D128800AT(L)-6
HYB25D128160AT(L)-6
DDR200
×
4
×
8
×
16
66 pin
TSOP-II
143
133
DDR266A
×
4
×
8
×
16
×
4
×
8
×
16
166
133
DDR333
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