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參數(shù)資料
| 型號： | HYB25D128400ATL-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 60/79頁 |
| 文件大?。?/td> | 2596K |
| 代理商： | HYB25D128400ATL-8 |
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HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Electrical Characteristics
Data Sheet
60
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
Internal write to read command delay
t
WTR
t
WTR1.5
1
2
80
200
—
—
—
—
—
7.8
1
—
75
200
—
—
—
—
—
7.8
t
CK
t
CK
ns
t
CK
μ
s
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read command
t
XSNR
Exit self-refresh to read command
Average Periodic Refresh Interval
t
XSRD
t
REFI
2)3)4)5)
2)3)4)5)14)
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
t
RPRES
is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 18
Parameter
AC Timing - Absolute Specifications –8/–7/-6
(cont’d)
Symbol
–8
–7
–6
Note/
Test Conditi
on
1)
DDR200
Min. Max.
DDR266A
Min.
DDR333
Min.
Max.
Max.
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| HYB25D128400CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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