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參數資料
| 型號： | HYB25D128400ATL-8 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數據速率SDRAM |
| 文件頁數： | 64/79頁 |
| 文件大?。?/td> | 2596K |
| 代理商： | HYB25D128400ATL-8 |
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HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Electrical Characteristics
Data Sheet
64
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
4.4.1
I
DD
Current Measurement Conditions
I
DD1
: Operating Current: One Bank Operation
1. Only one bank is accessed with
t
RC
(min) , Burst Mode, Address and Control inputs on NOP edge are changing
once per clock cycle.
I
OUT
= 0 mA.
2. Timing patterns
3.
DDR200
(100 MHz, CL = 2):
t
CK
= 10 ns, CL = 2, BL = 4,
t
RCD
= 2
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N R0 N N P0 N
Read : A0 N R0 N N P0 N - repeat the same timing with random address changing
50% of data changing at every burst changing at every burst
4.
DDR266
(133 MHz, CL = 2):
t
CK
= 7.5 ns, CL = 2, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 9
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N NN - repeat the same timing with random address changing
50% of data changing at every burst
5.
DDR333
(166 MHz, CL = 2.5):
t
CK
= 6 ns, CL = 2.5, BL = 4,
t
RCD
= 3
×
t
CK
,
t
RC
= 9
×
t
CK
,
t
RAS
= 5
×
t
CK
Setup: A0 N N R0 N P0 N N N
Read : A0 N N R0 N P0 N N N - repeat the same timing with random address changing
50% of data changing at every burst
6. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
I
DD7
: Operating Current: Four Bank Operation
1. Four banks are being interleaved with
t
RCMIN
. Burst Mode, Address and Control inputs on NOP edge are not
changing.
I
OUT
= 0 mA.
2. Timing patterns
a)
DDR200
(100 MHz, CL = 2):
t
CK
= 10 ns, CL = 2, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
, Read with
autoprecharge
Setup: A0 N A1 R0 A2 R1 A3 R2
Read: A0 R3 A1 R0 A2 R1 A3 R2 - repeat the same timing with random address changing
50% of data changing at every burst
b)
DDR266A
(133 MHz, CL = 2):
t
CK
= 7.5 ns, CL = 2, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
c)
DDR333
(166 MHz, CL = 2.5):
t
CK
= 6 ns, CL = 2.5, BL = 4,
t
RRD
= 2
×
t
CK
,
t
RCD
= 3
×
t
CK
Setup: A0 N A1 R0 A2 R1 A3 R2 N R3
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 - repeat the same timing with random address changing
50% of data changing at every burst
3. Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
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相關代理商/技術參數 |
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| HYB25D128400C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
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| HYB25D128400CE-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400CE-7 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
| HYB25D128400CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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