參數(shù)資料
型號： HYB25D128400ATL-8
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit Double Data Rate SDRAM
中文描述： 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù)： 6/79頁
文件大?。?/td> 2596K
代理商： HYB25D128400ATL-8
DDR333B
PC2700–2533
166
166
133
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Overview
Data Sheet
6
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
1
Overview
1.1
Features
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the
receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data. The x16 organization has two (LDM, UDM), one per byte.
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, (3)
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
15.6
μ
s Maximum Average Periodic Refresh
Interval
(4K refresh)
2.5V (SSTL_2 compatible) I/O
V
DDQ
= 2.5 V
±
0.2 V /
V
DD
= 2.5 V
±
0.2V
TSOP66 package
Table 1
Performance
1.2
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824
bits. It is internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data
rate architecture is essentially a
2n
prefetch architecture with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single
2n
-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-
clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned with data for Writes.
The 128Mb DDR SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
Part Number Speed Code
Speed Grade
–
6
–7
DDR266A
PC2100-2033
–
143
133
–
8
DDR200
PC1600-2022
–
125
100
Unit
—
—
MHz
MHz
MHz
Component
Module
@CL3
@CL2.5
@CL2
max. Clock Frequency
f
CK3
f
CK2.5
f
CK2
相關(guān)PDF資料
PDF描述
HYB25D128800AT-6 128 Mbit Double Data Rate SDRAM
HYB25D128800ATL-8 128 Mbit Double Data Rate SDRAM
HYB25D128400CC-6 128 Mbit Double Data Rate SDRAM
HYB25D128400CT-7 128 Mbit Double Data Rate SDRAM
HYB25D128800CT-6 128 Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128400C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM
HYB25D128400CC-6 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM
HYB25D128400CE-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128400CE-7 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM
HYB25D128400CT-7 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*