參數(shù)資料
型號： HYB25D128323CL-4.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁數(shù)： 9/53頁
文件大?。?/td> 1166K
代理商： HYB25D128323CL-4.5
Data Sheet
9
V1.7, 2003-07
128 Mbit DDR SGRAM
HYB25D128323C[-3/-3.3]
HYB25D128323C[-3.6/L3.6]
HYB25D128323C[-4.5/L4.5]
HYB25D128323C-5
1
Overview
1.1
Features
Maximum clock frequency up to 333 MHz
Maximum data rate up to 666 Mbps/pin
Data transfer on both edges of clock
Programmable CAS latency of 2, 3 and 4 clocks
Programmable burst length of 2, 4 and 8
Integrated DLL to align DQS and DQ transitions with CLK
Data transfer signals are synchronized with byte wise bidirectional Data Strobe
Data Strobe signal edge-aligned with data for Read operations
Data Strobe signal center aligned with data for Write operations
Differential clock inputs (CLK and CLK)
Data mask for masking write data, one DM per byte
Organization 1024K
×
32
×
4 banks
4096 rows and 256 columns per bank
4K Refresh (32ms)
Refresh Interval 7.8 μsec
Autorefresh and Self Refresh available
Standard JEDEC TF-XBGA 128 package
Self-mirrored, symmetrical ball out
Matched Impedance Mode interface (Z
0
=60
)
SSTL-2 JEDEC Weak Mode interface (Z
0
=34
)
IO voltage
V
DDQ
= 2.5 V
V
DD
power supply memory core:
– Speed sorts –3 and –3.3: 2.5 V <
V
DD
< 2.9 V
– Speed sorts L4.5, –4.5, and –5:
V
DD
= 2.5 V
– Speed sorts L3.6 and –3.6 support both
V
DD
modes
1.2
Description
The Infineon 128Mbit DDR SGRAM is a ultra high performance graphics memory device, designed to meet all
requirements for high bandwidth intensive applications like PC graphics systems.
The 128Mbit DDR SGRAM uses a double-data-rate DRAM architecture organized as 4 banks
×
4096 rows
×
256
columns
×
32 bits. The double-data-rate architecture is essentially a 2n prefetch architecture, with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single Read or Write access to the DDR
Table 1
Part Number Speed Code
CAS Latency 4
Performance
–
3
3
333
4.0
250
1.05
0.30
–
3.3
3.3
300
4.0
250
1.15
0.30
–
3.6
3.6
278
4.2
238
1.26
0.33
–
4.5
4.5
222
4.5
222
1.58
0.45
–
5.0
5.0
200
5.0
200
1.75
0.5
L3.6
3.6
278
4.2
238
1.26
0.33
L4.5
4.5
222
4.5
222
1.58
0.45
Unit
ns
MHz
ns
MHz
ns
ns
t
CK4min.
f
CK4max.
t
CK3min.
f
CK3max.
t
QH
t
DQSQ
CAS Latency 3
Data Out Window
DQS-DQ Skew
相關(guān)PDF資料
PDF描述
HYB25D128323CL3.6 128 Mbit DDR SGRAM
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HYB25D128323C-5 128 Mbit DDR SGRAM
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