參數(shù)資料
型號(hào)： HYB25D128323CL-4.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 20/53頁(yè)
文件大?。?/td> 1166K
代理商： HYB25D128323CL-4.5
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
20
V1.7, 2003-07
3.5
Description of Timings
3.5.1
The following sequence is highly recommended for Power-Up:
1. Apply power and start clock. Maintain CKE=L and the other pins are in NOP conditions at the input
2. Apply
V
DD
before or at the same time as
V
DDQ
, apply
V
DDQ
before or at the same time as
V
REF
&
V
TT
3. Start clock, maintain stable conditions for 200
μ
s min.
4. Apply NOP and set CKE to high
5. Apply a Precharge All command
6. Issue EMRS (extended mode register set) command to enable the DLL
7. Issue a Mode Register Set command for “DLL reset“. 200 cycles of clock input are required to lock the DLL.
8. Issue Precharge commands for all banks of the device.
9. Issue two or more Auto-Refresh commands.
10.Issue a Mode Register Set command. (This step may also be taken as step 6)
Power-Up Sequence
Figure 9
Power-Up Sequence
3.5.2
The DDR SGRAM should be activated with CKE already high prior to writing into the mode register. Two clock
cycles are required to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state.
Mode Register Set Timing
Figure 10
Mode Register Set Timing
3.5.3
The timing of the Extended Mode Register Setup operation is equivalent to the Mode Register Setup timing.
Extended Mode Register Set Timing
Clock
Command
EMRS
PREA
DLL
PREA
ARef
ARef
MRS
any
Comm.
t
MRD
200 Clock min.
t
RP
t
RFC
t
RFC
t
MRD
t
RP
NOP
2 Clock
min.
Clk
Command
t
RP
t
MRD
NOP
PREA
NOP
MRS
NOP
Comm.
any
NOP
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