參數(shù)資料
型號: HYB25D128323CL-4.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit DDR SGRAM
中文描述: 128兆的DDR SGRAM
文件頁數(shù): 50/53頁
文件大?。?/td> 1166K
代理商: HYB25D128323CL-4.5
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Electrical Characteristics
Data Sheet
50
V1.7, 2003-07
Table 24
Frequency /
t
CK
278 MHz / 3.6 ns
HYB25D128323CL3.6
CAS latency
4
t
RC
13
t
RFC
15
t
RAS
9
t
RP
4
t
WR
2
t
RRD
3
t
DAL
6
t
RCDRD
4
t
RCDWR
2
Units
t
CK
250 MHz / 4.0 ns
4
13
15
9
4
2
3
6
4
2
t
CK
222 MHz / 4.5 ns
3
12
14
8
4
2
2
6
4
2
t
CK
200 MHz / 5.0 ns
3
10
12
7
3
2
2
5
3
2
t
CK
166 MHz / 6.0 ns
3
9
11
6
3
2
2
5
3
2
t
CK
Table 25
Frequency /
t
CK
222 MHz / 4.5 ns
HYB25D128323CL4.5
CAS latency
3
t
RC
12
t
RFC
14
t
RAS
8
t
RP
4
t
WR
2
t
RRD
2
t
DAL
6
t
RCDRD
4
t
RCDWR
2
Units
t
CK
200 MHz / 5.0 ns
3
12
14
8
4
2
2
6
4
2
t
CK
183 MHz / 5.5 ns
3
12
14
8
4
2
2
6
4
2
t
CK
166 MHz / 6.0 ns
3
10
12
7
3
2
2
5
3
2
t
CK
143 MHz / 7.0 ns
3
9
11
6
3
2
2
5
3
2
t
CK
Table 26
Parameter & Test Condition
Operating Currents
Symbol
–3
max.
200
–3.3
–3.6
–4.5
–5.0
L3.6
typ.
L4.5
typ.
Unit Notes
OPERATING CURRENT: One bank;
Active-Precharge;
t
RC
=
t
RC(min.)
;
t
CK
=
t
CK(min.)
; DQ, DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two clock cycles
OPERATING CURRENT:
One bank;
Active-Read-Precharge; BL=4; CL=4;
t
RCDDC
= 4*
t
CK
;
t
RC
=
t
RC(min.)
;
t
CK
=
t
CK(min.)
;
I
OUT
= 0mA; Address and
control inputs changing once per clock
cycle
PRECHARGE POWER-DOWN
STANDBY CURRENT: All banks idle;
power-down mode;
t
CK
=
t
CK(min.)
;
CKE=LOW
I
DD0
190
180
160
150
mA
1)
I
DD1
230
220
110
190
180
mA
I
DD2P
26
22
22
14
14
10
7
mA
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