參數(shù)資料
型號(hào): HYB25D128323CL-4.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit DDR SGRAM
中文描述: 128兆的DDR SGRAM
文件頁(yè)數(shù): 36/53頁(yè)
文件大?。?/td> 1166K
代理商: HYB25D128323CL-4.5
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
36
V1.7, 2003-07
Note:The Power Down Mode Entry command is illegal during Burst Read or Burst Write operations.
3.8
Function Truth Tables
Table 10
lists all abbreviations used in
Table 11
and
Table 12
.
Power Down Mode Entry
(Note)
Power Down Mode Exit
PWDNEN
H
H
L
L
L
H
H
L
H
L
X
H
X
valid
X
H
X
valid
X
H
X
valid
X
X
X
X
X
X
X
X
X
X
X
X
PWDNEX
Table 10
H
L
X
V
RA
BA
PA
NOP
CA
Ax
Abbreviations
High Level
Low Level
Don’t Care
Valid Data Input
Row Address
Bank Address
Precharge All
No Operation
Column Address
Address Line x
Table 11
Current State
IDLE
Function Truth Table I
Command
DESEL
NOP
BST
READ / READA
WRITE / WRITEA
ACT
PRE / PREAL
AREF / SREF
MRS / EMRS
Address
X
X
X
BA,CA,A8
BA,CA,A8
BA, RA
BA, A8
X
Op-Code
Action
NOP
NOP
NOP
ILLEGAL
ILLEGAL
Bank Active
NOP
AUTO-Refresh or Self-Refresh
Mode Register Set or Extended Mode
Register Set
Notes
3)
1)
3)
3)
2)
3)
3)
1)
4)
1)
1)
1)
4)
5)
4)
Table 9
Operation
Command Overview
(cont’d)
Code
CKE
n-1
CKE
n
CS#
RAS# CAS# WE#
BA0
BA1
A8
A0-7
A9-11
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