參數(shù)資料
型號(hào)： HYB25D128323CL-4.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 34/53頁(yè)
文件大?。?/td> 1166K
代理商： HYB25D128323CL-4.5
masked
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
34
V1.7, 2003-07
3.6.5
A Burst Write can be interrupted by a Read command sent to any bank. The DQs must be in the high impedance
state at least one clock cycle before the data of the interrupting read appears on the outputs to avoid data
contention. Before the Read Command is registered, any residual data from the burst write cycle must be masked
by DMx. Data that is presented on the DQ pins before the Read command is initiated, will actually be written to
the memory.
Write Interrupted by a Read
Figure 28
Write interrupted by Read
3.6.6
A Burst Write operation can be interrupted before completion of the burst by a Precharge of the same bank.
Random column access is allowed. A Write Recovery time (
t
WR
) is required from the last data to Precharge
command. When Precharge command is asserted, any residual data from the burst write cycle must be masked
by DMx.
Write Interrupted by a Precharge
NOP
D-in
2
CLK
Write
DQSx
DQx
D-in
0
Command
t
WTR
DMx
CL = 2
NOP
NOP
Read
NOP
NOP
D-in
1
D-in
3
t
DQSS
D-out
0
D-out
1
Last valid
data
Data must be
Burst length = 8
CL = 2
Data is masked
by Read
D-in
4
D-in
5
相關(guān)PDF資料
PDF描述
HYB25D128323CL3.6 128 Mbit DDR SGRAM
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HYB25D128323C-3.6 128 Mbit DDR SGRAM
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HYB25D128323C-5 128 Mbit DDR SGRAM
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