Pin Name
I/O
Option
Description
XT1
XT2
I
O
32768Hz crystal across XT1 and XT2 will generate RTC clock signal which
only provides system timing.
CMPN
I
Negative input for comparator
CMPP
I
Positive input for comparator
CMPO
O
Comparator output
CHGO
O
Comparator output with 32768Hz carrier
VDD
Positive power supply
AVDD
A/D converter Positive power supply, AVDD should be externally con-
nected to VDD
VSS
Negative power supply, ground
RES
I
Schmitt trigger reset input
OSC1
OSC2
I
O
RC or crystal
A resistor across OSC1 and VDD or a crystal across OSC1 and OSC2 will
generate a system clock.
VLCD
I/O
LCD highest voltage; should be connected to VDD with external resistor.
SEG0~SEG18
O
SEG7~SEG18
logical CMOS
LCD segment signal driving outputs SEG7~SEG10 can be optioned as out-
put lines. SEG11~SEG14, SEG15~SEG18 can be optioned as a high sink-
ing output lines.
COM0~COM3/
SEG19
O
COM3 or
SEG19
LCD common signal driving outputs
Absolute Maximum Ratings
Supply Voltage...........................V
SS
0.3V to V
SS
+5.5V
Storage Temperature............................ 50 C to 125 C
Input Voltage..............................V
SS
0.3V to V
DD
+0.3V
Operating Temperature........................... 25 C to 70 C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25 C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
V
LCD
LCD Highest Voltage
0
V
DD
V
I
DD1
Operating Current (RC OSC)
(Analog circuit disabled)
3V
No load, f
SYS
=4MHz
0.6
1.5
mA
5V
2
4
I
DD2
Operating Current (RC OSC)
3V
No load, f
SYS
=4MHz
0.8
1.5
mA
5V
2.5
4
I
DD3
Operating Current (Crystal OSC)
5V
No load, f
SYS
=8MHz
3
5
mA
I
STB1
Standby Current
(WDT OSC On, RTC Off, LCD Off)
3V
No load,
System HALT
5
A
5V
15
HT46R63/HT46C63
Rev. 1.00
5
September 9, 2002