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參數(shù)資料
| 型號： | HT46C63(100QFP) |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 23/42頁 |
| 文件大小： | 362K |
| 代理商： | HT46C63(100QFP) |
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HT46R63/HT46C63
Rev. 1.00
23
September 9, 2002
Label
(ACSR)
Bits
Functions
ADCS0
ADCS1
0
1
ADCS1, ADCS0: Selects the A/D converter clock source
0,0: f
SYS
/2
0,1: f
SYS
/8
1,0: f
SYS
/32
1,1: Cannot be used
CMPC
2
Comparator control (*)
0: Disable
1: Enable
3~6
Unused bit, read as 0
TEST
7
For test mode used only
0: Normal mode
1: TEST only, cannot be used
Note:
* This bit is 0 during reset.
I
/
I I
/
4
/
/
8 $
"
$ - $ #
#
#
/
'
" + $ - & "
$ - $ # /
'
" + $ # $
#
#
/
'
" + $ - & "
$ - $ # /
'
" + $ # $
4 " .
/
'
" + $ # $
4 " .
/
'
" + $ # $
A
$ & " $
'
" & !
# & "
A
$ , $ ' #
"
,
' 0
" " $ ,
I I I
A
$ , $ ' # /
' , ' (
9 4 <
% , $ A
' 0
" " $ , 6 /
6
) :
A / , ,
, & " $ & - . & & # , & " % ! #
A /
'
" + $ # $
& - %
8 $
#
$ . ! ' $ %
8 $
'
" - ! % # & "
I
/
B I B /
'
" + $ # & "
# & $ & -
/
B I I B
$
" - .
" C# '
$
B I I I B /
' , ' ( ! - # $
6
) 6
# $ A
A/D conversion timing
PWM
The micro-controller provides 4 channels (6+2) bits
PWM outputs shared with PD0~PD3. The PWM chan-
nels has their data register. The PWMs uses a PWM
counter whose stages are 8 (stage 1~stage 8: f
SYS
/2
1
~
f
SYS
/2
8
). The frequency source of the PWM counter co-
mes from f
SYS
. The PWM register is an eight bits regis-
ter. The waveforms of PWM outputs are as shown.
Once the PDi (i=0~3) is selected as the PWMi output
and the output function of PDi is enabled, writing 1 to
PDi data register will enable the PWMi output function.
Otherwise the PDi will stay at 0 . The PWM modulation
frequency, PWM cycle frequency and PWM cycle duty
are summarized in the following table.
PWMi Modulation
Frequency
PWMi Cycle
Frequency
PWMi Cycle
Duty
f
SYS
/64
f
SYS
/256
[PWM]/256
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