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參數(shù)資料
| 型號(hào)： | HT46C63(100QFP) |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 30/42頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HT46C63(100QFP) |
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CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i
0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are
cleared.
Operation
WDT
00H
PD and TO
0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
0
0
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT
00H*
PD and TO
0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
0*
0*
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of
this instruction without the other preclear instruction, sets the indicated flag which implies
this instruction has been executed and the TO and PD flags remain unchanged.
Operation
WDT
00H*
PD and TO
0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
0*
0*
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1 s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m]
[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
HT46R63/HT46C63
Rev. 1.00
30
September 9, 2002
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